VLS

تصميم الدوائر المتكاملة

اكتب Verilog لمعالج 4 بت: محاكاة وموجات وتخليق وتوقيت — وصدّره Icarus Verilog وYosys.

التجربة:0/100الـfull adder مبني من xor و and و or — بس بوابة الحامل اتبدّلت. صلّحها وخلّي الجمع يطلع صح.

افتح تجربة .bsim

1. افتح المخطط
2. بوابة الحامل
3. شوف الحامل في الموجة
4. اكسر وصلّح: vls.sum-no-cin
5. العقد كله أخضر
6. صدّر مشروع Icarus Verilog

افتح المخطط: افتح «المخطط»: core فيه alu4 جواه adder4 جواه 4 نسخ full_adder.

المحاكاة

على البوابات (بعد التخليق)

13 نسخة · 108 إشارة · ساعة 100 MHz — اختار سيناريو ودوس «شغّل».

المفتش

شغّل سيناريو الأول عشان تشوف الموجة.

design.v

`default_nettype none
// Basma VLSI: a 4-bit accumulator core — gates -> adder -> ALU -> registers -> FSM.
// basma: clock_mhz 100

// 1-bit full adder from gate primitives
module full_adder (
    input  wire a,
    input  wire b,
    input  wire cin,
    output wire sum,
    output wire cout
);
  wire p, g, t;
  xor x1 (p, a, b);
  xor x2 (sum, p, cin);
  and a1 (g, a, b);
  and a2 (t, p, cin);
  and o1 (cout, g, t);
endmodule

// 4-bit ripple-carry adder: four full adders in a chain
module adder4 (
    input  wire [3:0] a,
    input  wire [3:0] b,
    input  wire       cin,
    output wire [3:0] sum,
    output wire       cout,
    output wire       c3
);
  wire c1, c2;
  full_adder fa0 (.a(a[0]), .b(b[0]), .cin(cin), .sum(sum[0]), .cout(c1));
  full_adder fa1 (.a(a[1]), .b(b[1]), .cin(c1), .sum(sum[1]), .cout(c2));
  full_adder fa2 (.a(a[2]), .b(b[2]), .cin(c2), .sum(sum[2]), .cout(c3));
  full_adder fa3 (.a(a[3]), .b(b[3]), .cin(c3), .sum(sum[3]), .cout(cout));
endmodule

// ALU: op 0 ADD, 1 SUB, 2 AND, 3 OR, 4 XOR, 5 SHL, 6 LOAD, 7 HALT (y = a)
// flags = {z, c, n, v}; SUB is a + ~b + 1 (c = 1 means no borrow)
module alu4 (
    input  wire [2:0] op,
    input  wire [3:0] a,
    input  wire [3:0] b,
    output reg  [3:0] y,
    output wire [3:0] flags
);
  localparam ADD = 3'd0, SUB = 3'd1, AND = 3'd2, OR = 3'd3;
  localparam XOR = 3'd4, SHL = 3'd5, LOAD = 3'd6;
  wire [3:0] sum, dif;
  wire cs, cs3, cd, cd3;
  adder4 add (.a(a), .b(b), .cin(1'b0), .sum(sum), .cout(cs), .c3(cs3));
  adder4 subt (.a(a), .b(~b), .cin(1'b1), .sum(dif), .cout(cd), .c3(cd3));
  reg c, v;
  always @(*) begin
    c = 1'b0;
    v = 1'b0;
    case (op)
      ADD: begin
        y = sum;
        c = cs;
        v = cs3 ^ cs;
      end
      SUB: begin
        y = dif;
        c = cd;
        v = cd3 ^ cd;
      end
      AND: y = a & b;
      OR: y = a | b;
      XOR: y = a ^ b;
      SHL: begin
        y = {a[2:0], 1'b0};
        c = a[3];
      end
      LOAD: y = b;
      default: y = a;
    endcase
  end
  assign flags = {y == 4'd0, c, y[3], v};
endmodule

// 7-segment decoder (segments gfedcba, 1 = on)
module seg7 (
    input  wire [3:0] d,
    output reg  [6:0] seg
);
  always @(*) begin
    case (d)
      4'h0: seg = 7'b0111111;
      4'h1: seg = 7'b0000110;
      4'h2: seg = 7'b1011011;
      4'h3: seg = 7'b1001111;
      4'h4: seg = 7'b1100110;
      4'h5: seg = 7'b1101101;
      4'h6: seg = 7'b1111101;
      4'h7: seg = 7'b0000111;
      4'h8: seg = 7'b1111111;
      4'h9: seg = 7'b1101111;
      4'ha: seg = 7'b1110111;
      4'hb: seg = 7'b1111100;
      4'hc: seg = 7'b0111001;
      4'hd: seg = 7'b1011110;
      4'he: seg = 7'b1111001;
      4'hf: seg = 7'b1110001;
      default: seg = 7'b0000000;
    endcase
  end
endmodule

// The core: IDLE -go-> RUN (one instruction per clock) -HALT-> HALT -!go-> IDLE
module core (
    input  wire       clk,
    input  wire       rst,
    input  wire       go,
    input  wire [2:0] op,
    input  wire [3:0] b,
    output reg  [3:0] acc,
    output reg  [3:0] flags,
    output reg  [3:0] pc,
    output reg  [1:0] state,
    output reg  [3:0] prev,
    output wire [3:0] y,
    output wire [6:0] seg
);
  localparam IDLE = 2'd0, RUN = 2'd1, HALT = 2'd2;
  localparam OP_HALT = 3'd7;
  wire [3:0] f;
  alu4 alu (.op(op), .a(acc), .b(b), .y(y), .flags(f));
  seg7 disp (.d(acc), .seg(seg));
  always @(posedge clk or posedge rst) begin
    if (rst) begin
      state <= IDLE;
      acc   <= 4'd0;
      flags <= 4'd0;
      pc    <= 4'd0;
      prev  <= 4'd0;
    end else begin
      case (state)
        IDLE: if (go) state <= RUN;
        RUN:
        if (op == OP_HALT) state <= HALT;
        else begin
          prev  <= acc;
          acc   <= y;
          flags <= f;
          pc    <= pc + 4'd1;
        end
        HALT: if (!go) state <= IDLE;
        default: state <= IDLE;
      endcase
    end
  end
endmodule

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العقد واختبارات الوحدات

14 سيناريو — لسه ما شغّلتش على النسخة دي.

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